module div2(clock,rst,clk_out2);
input clock,rst;
output clk_out2;
reg [15:0] m;
reg clk_out2;
always @(posedge clock)
begin
	if(!rst)
	begin clk_out2<=0; m<=0; end
	else
	begin
		m<=m+1;
		if(m==24999) clk_out2<=~clk_out2;
		if(m==49999) begin clk_out2<=~clk_out2; m<=0; end
	end
end
endmodule